The present invention relates generally to fabricating low resistivity conductive lines and electrodes, and more specifically to fabricating low resistivity conductive lines and electrodes using near noble metals and their compounds.
Metal Oxide Semiconductor (MOS) devices are widely used today in ultra large scale integrated (ULSI) devices. MOS devices include memory devices which are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. Long conductors, referred to as word lines, serve as gates of multiple access transistors, each of which provides access to a memory cell.
In a dynamic random access memory (DRAM) a common word line is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide (SiO2), known as gate oxide. Word lines currently are formed on the gate oxide layer as a two-layer stack, comprising silicon (or polysilicon), coated with a conductor material such as tungsten silicide or titanium silicide.
Of primary concern is minimizing resistivity throughout the word line due to the need to reduce RC time constants and access multiple memory cells in as short a period of time as possible. The problem is especially critical due to the extended length of word lines as DRAMs increase in density.
As DRAM density increases, feature sizes, including line sizes, decrease. For example, when the feature size of a conductor, such as tungsten or titanium silicides, is reduced in higher density memories, the Kelvin contact resistance of the conductor increases. Titanium silicide is a large grain material. Thin titanium silicide has nonuniform large grain size that contributes to a very rough titanium silicide/silicon interface. As such, it reduces the effective ohmic contact area. It is therefore desirable to utilize conductors that have smaller grains and hence whose resistivity will not significantly increase for the same feature dimensions.
Conductors utilizing near noble metal suicides, such as CoSi2 have low bulk resistivity and a fine grain with very small line-width dependent Rs effects. They are well suited for sub-quarter micron conductor formation such as polycide word lines or bit lines. However, they are very difficult to pattern because of the nonvolatile nature of cobalt fluorides and chlorides during a dry etch process. Conventional methods of patterning CoSi2 polycide gate electrodes for DRAM devices require extra masks to pattern insulating layers or spacers. A Co salicidation is then used on fill-in Si (poly), The extra masks can significantly increase costs of DRAM devices.
There is a need to decrease the overall resistivity of a word line stack and local interconnects at sub-quarter micron dimensions. There is a need to precisely pattern CoSi2 conductors and word line stacks without introducing additional masks.
There is a further need to precisely etch such conductors and word line stacks in an inexpensive manner.
A method for forming conductive lines for a semiconductor device, comprises forming a blanket stack on a substrate including a conductive diffusion barrier, a near noble metal such as cobalt, followed by a silicon layer and a top insulator layer. The blanket stack is patterned with resist to define the conductive lines. The stack is etched down to the near noble metal layer. The resist is then removed and the stack is annealed to react the near noble metal and semiconductor to form a conductive compound having fine grain size. The unreacted noble metal is then etched, using the conductive diffusion barrier as an etch stop.
In one embodiment, a further etch is then performed down to the substrate, using the top insulator layer as a mask. In this manner, only one mask is required to form the conductive line.
In one embodiment, the semiconductor device comprises a DRAM (Dynamic Random Access Memory) device, and the conductor is a CoSi2 gate stack. The heating step comprises an anneal at temperatures in excess of approximately 550 degrees Celsius, or at least great enough to react the cobalt and silicon. The gate stack also serves as a word line for the DRAM device. The word line width is sub-quarter micron.
In a further embodiment, the cobalt is etched using a wet etch process which has a high selectivity with respect to CoSi2. The conductive diffusion barrier comprises tungsten nitride or titanium nitride and acts as a stop for the wet etch with at least of portion of it also being etched. The further etch to the substrate is performed using a common dry etch. Further standard process flow is followed to complete the semiconductor device.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.